Circuit Design
(Source: Self-created in Logisim)
The Q1 design was designed on the basis of basic logic parts, that is, the use of 2-input AND, and 2-input OR gates, and a single-input NOT gates only. These gates were implemented in the Legisim 7400 library using the standard 7400-series integrats supportable on hardware. The chips chosen were 7404 Hex Inverter to used logical negation, 7408 Quad 2-input AND used conjunctions and Quad 2-input OR used disjunctions.
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The connexions were directed by the simplified Boolean expressions. Segments a and d are constant and as such linked to logic assurance, and thus kept on. S0 has a direct control over segment b. Segment f is advected using the opposite of S0 in one gate of the 7404 (Kanan et al. 2023). Then e: Segments e needs two inverted and combined inputs, and thus !S1 and !S0 are fed through two invertors and into a AND gate. Lastly, both the segments c and g are governed by the same expression, namely, S 0 + S 1 and thus are controlled by only one output of an OR gate.
Logisim Implementation
The developed design was deployed in Logisim with the 7400 library. The outputs a-g was connected to a seven-segment display, inputs S0 and S1 were done as switches, and other interfaces were not connected at all (Vurkac et al. 2024). It was later seen with simulation that all input combinations would show the right digits.
Circuit Design
(Source: Self-created in Logisim)
For Q2, the entire student figure should be entered so three selecting switches (S2, S1, S0) should be used. This is where limitations of types of gates are challenged, and thus there are allowed to be the use of generic gates (Höltgen et al. 2021). The Karnaugh map simplification provided the Boolean expressions of each segment and these were simply translated by means of a combination of the gates of NOT, AND, and OR.
Multi-input AND and OR gates were employed where possible, as opposed to concatenating several 2-input gates, to minimise the number of gates. Indicatively, segment c, which can be characterised as S0 + S1 + S2 was realised with only one 3-input OR gate. In the same way, segment e called 3-pegged 3-input ANDgate, was implemented with S0S1S2. This strategy will keep the design tight and logically minimal.
Moreover, typical sub-expressions were recognised and reomused among various outputs. As example, ¬S0 was successively attacked in several portions and one inverter was installed, and its output was disseminated at the place where it was needed. Such reuse prevented duplication and scaled-down the number of gates needed by the end circuit.
Logisim Implementation
Well the simplified circuit was contained in Logisim by use of the standard gate library. The three inputs were referred to as S2, S1, and S0 and outputs a-g as outputs efficiently linked to a seven digit display component (Wang and Zhao 2023). Systematic testing of each segment expression in all the selector values (000 to 111) was done. This was validated by simulation using seven-seg which displayed correctly the digits of the student ID, which verified the accuracy of circuit design.
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Reference List
- Wang, G., & Zhao, Y. (2023, June). Enhancing Teaching Effectiveness and Learning Experience of Digital Circuit Design using Multiple Tools. In 2023 ASEE Annual Conference & Exposition. Retrieved From: https://peer.asee.org/43371.pdf [Retrieved On: 1.9.25]
- Kanan, A., Alqudah, R. A. J. A. A., & Al-mousa, A. (2023). A Systematic Multi-Level Assessment Approach to Enhance Students’ Academic Performance in Sequential Logic Design. International Journal of Engineering Education, 39(5), 1256-1267. Retrieved From: https://www.researchgate.net/profile/Amjed-Almousa/publication/378156221_A_Systematic_Multi-Level_Assessment_Approach_to_Enhance_Students'_Academic_Performance_in_Sequential_Logic_Design/links/65cafad07900745497817cd2/A-Systematic-Multi-Level-Assessment-Approach-to-Enhance-Students-Academic-Performance-in-Sequential-Logic-Design.pdf [Retrieved On: 1.9.25]
- Vurkac, M., Takach, M. D., & Singh, S. (2024, June). Digital Logic without Compromise in a Quarter-Based EE Curriculum. In 2024 ASEE Annual Conference & Exposition. Retrieved From: https://peer.asee.org/digital-logic-without-compromise-in-a-quarter-based-ee-curriculum.pdf [Retrieved On: 1.9.25]
- Höltgen, S., Fecker, T., Pleikies, S., Wormsbecher, N. and Divani, S., 2021. A Case of Toy Computing Implementing Digital Logics with “Minecraft”. Andrew Adamatzky (Hg.): Alternative Computing. Heidelberg et al.: Springer. Retrieved From: https://www.researchgate.net/profile/Stefan-Hoeltgen/publication/346037802_A_Case_of_Toy_Computing_Implementing_Digital_Logics_with_Minecraft/links/5fb7de9792851c933f4731d8/A-Case-of-Toy-Computing-Implementing-Digital-Logics-with-Minecraft.pdf [Retrieved On: 1.9.25]
